The results of this work can then be exploited to identify when Lu’s method is preferable with respect to Forney’s method, depending on the platform chosen to implement the whole decoder. This method was adopted as a benchmark as it is, to date, the most implemented in RS decoders, and is considered the most efficient method. To properly compare the results, the Forney method was deployed on the same platforms and its behavior was assessed as well. The performance is evaluated in terms of processing time (in both MCU and FPGA implementations) and area (for the FPGA only). For this purpose, two different platforms were considered, an FPGA (field programmable gate array) and an MCU (microcontroller unit), to evaluate the behavior over different possible solutions: the first fully parallel and the latter fully sequential. The aim of this paper is to complete Lu’s theoretical work applying two different implementation strategies to the method and estimating the performance.

However, to the best of our knowledge, this algorithm has not yet been implemented and only a theoretical description is provided in the literature. , allowing the same result to be obtained with less system complexity and computational effort. Then, an innovative method has been proposed by Lu et al. Komo and Joiner proposed an iterative algorithm in the work of based on a Vandermonde matrix, which results in an improvement of the processing speed of about 2.8 times compared with the Forney method. A traditional implementation exploits the Forney method. Among them, many research works focus on the optimization of error magnitude evaluation. Several approaches have been proposed to improve the performance of the decoder. Most of the works in the literature focus on the decoder part, as it holds the most complex operations. Īs all communication systems, RS ECCs are composed of an encoder at the sender side and a decoder at the receiver side. RS codes are among the most implemented solutions in a wide set of areas, such as data storage, bar and QR (quick response) codes, space and TV transmission, and so on. A subset of BCH codes are Reed–Solomon (RS) codes, which ease the implementation in binary encoded messages. By exploiting the multiplication, the addition, and the inversion defined in the field, the system can be configured to correct the desired amount of errors in the message by increasing the parity information appended to the message itself. They solve the limitation of the maximum correctable errors by introducing Galois Fields. To improve Hamming codes, Bose–Chaudhuri–Hocquenghem (BCH) codes were presented in the works of. Hamming ECCs can correct up to one error in the message and are characterized by low parity information, which makes them suitable for applications requiring high data rates, but low error occurrence. Among them, Hamming error correction codes (ECCs) were one of the first introduced, in 1950, to correct errors in punched card readers. The results show that the theoretical finding are fully confirmed only in the MCU implementation, while on FPGA, the choice of one method with respect to the other depends on the optimization feature (i.e., time or area) that has been decided as a preference in the specific application.Ĭonsiderable research work has been done on this topic, and a variety of systems based on different algorithms have been proposed. As a benchmark in the analysis, the well-established Forney’s method is exploited: it has been implemented in the same configurations and on the same hardware platforms for a proper comparison. The performances have been evaluated in terms of resource usage and output delay for the FPGA and in terms of code execution time for the MCU. Several configurations of the encoded message chosen between those typically used in different applications have been designed to be run on an FPGA (field programmable gate array) device and an MCU (microcontroller unit). under different systems configurations and hardware platforms. This paper aims to assess the performance of an innovative algorithm introduced in the literature by Lu et al. RS decoders are composed of several blocks: among them, many efforts have been made to optimize the error magnitude evaluation module. Reed–Solomon (RS) codes are one of the most used solutions for error correction logic in data communications.

Dpo7254 signal path compensation error